On Raspberry Pi USB ports
All quoted text is from:
Raspberry Pi USB Hardware Documentation
Please note, that I have all models of the RPi including the Pi Zero and Zero W but not the 4… and have done extensive experimentation over the last 6 or 7 years on each of the boards I have acquired. This does not make me an expert in any way, and I’m not sure I respect those who claim to be experts anyway.
Pi Hardware
In all models prior to the Pi 4, the USB ports connect to a combo hub/Ethernet chip, which is itself a USB device connected to the single upstream USB port on BCM2835. On the Pi 4, the USB hub chip is connected to the SoC using a PCIe bus.
Thus, all RPi models other than the Pi 4 will very likely experience significant performance issues when used as a Storj Node. The shared bus bandwidth and processing resources will necessarily slow down data transfers to/from BOTH the USB and Ethernet ports. This will most likely result in any given RPi node (other than a model 4) processing network requests far slower than any other platform/node running in the same WAN subnet.
For the Pi 4, a fully-featured host controller drives the downstream USB ports. Downstream USB is provided by a Via Labs VL805 chip
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this is connected to the BCM2711 SoC using a PCIe link, which is extremely fast.
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All connected USB 2.0 devices are connected via an internal hub which connects to the upstream PCIe link via a single USB 2.0 bus, giving a maximum combined bandwith for all USB 2.0 devices of 480Mbits/s.
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USB 3.0 ports (blue) are ALSO connected to the USB 3.0 bus via the USB 3.0 specific pins in the socket. USB 3.0 devices are constrained only by the total bandwidth available over the PCIe link.
Therefore, in order to have any improvement in performance using an RPi 4, one must use a USB 3.0 External HDD. All USB 2.0 External HDD are going to suffer bandwidth constraints similiar to all prior RPi USB connected devices. However… the precise speed of the PCIe link is not ennumerated in any documentation I could find… nor is the bus width indicated.
Unfortunately, the RPi documentation is very poor. Broadcom is quite overprotective of their chip designs even so much as to deny the Open Source community the ability to boot their chips without their proprietary binary blob tainting the Linux kernel.
My guess is that the RPi 4 PCIe bus width is simulated through internal multiplexing and the bus speed is constrained by both the complexity of the internal circuitry as well as the parasitic operational noise on the board itself. All-in-all the RPi boards are excellent hobbyist tools for experimentation, but are unsuitable for any production environment application.
However… an old netbook running some USB connected drives may provide similar low power requirements but much better data piece catching success. Don’t know, haven’t tested it…